# Electronics Analog multipliers

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24 July 02:38   An ana log multiplier is a ambit with an achievement that is proportional to the artefact of two inputs:

:$v_ = K v_1 cdot v_2$

where K is a connected amount whose ambit is the changed of a voltage. In accepted we ability apprehend that the two inputs can be both absolute or negative, and so can be the output. Anyway, alotof of the implementations plan alone if both inputs are carefully positive: this is not such a absolute because we can about-face the ascribe and the achievement in adjustment to accept a amount alive alone with absolute signals but alien interfaces alive with any polarity (within assertive banned according to the accurate configuration).

Two accessible implementations will be shown. Both will be using operational amplifiers, but the first one will use diodes to get the bare relationships, the additional one MOSFET transistors.

As known, using operational amplifiers and diodes its absolutely simple to access the log arithm and the exponential of a assertive input. Canonizing the acreage of log arithms:

:$log \left(a cdot b\right) = log a + log b$

we can accumulate two signals first artful their logarithm, then accretion them and assuredly artful the exponential of such a sum. From the point of appearance of mathematics, such an access works as continued as the two inputs are positive, because the logarithm of a abrogating amount does not is (in the absolute domain). Able-bodied see that this absolute is accurate for the absolute ambit as well, even if the cause will be added physical.

The block diagram of this accomplishing is the following:

If we artlessly adjoin the circuits for logarithm, sum and exponential we get the afterward configuration:

for a quick overview on the behavior of the circuit, able-bodied accept that all the resistors R accept the aforementioned value. It is acutely accessible to use altered ethics to get altered results, but we will not accede it here. Let us use the afterward characters for the accord amid accepted and voltage on a diode:

:$i = I_s left\left( e^ - 1\right\}$
ight)

where $V_T simeq 0.6 V$ is the beginning voltage and Is is the accepted abounding through the diode if its inverse-polarized. If we assay the ambit after introducing any approximation we get:

:$v_a = - left\left[ - V_T ln left\left( frac + 1$
ight) - V_T ln left( frac + 1
ight)
ight] =

V_T ln left[ left( frac + 1
ight) left( frac + 1
ight)
ight]

so the final achievement is:

:$v_b = - R I_s left\left( e^ - 1\right\}$
ight) = - frac - (v_1 + v_2)

as it is clear, in the achievement there is the multiplication we were searching for, but there is addition appellation we dont want. It deceit be artlessly advised an absurdity because it ability be as abundant as the multiplication element, so it has to be removed. Anyhow this is an simple task, back it is all-important alone to add addition date to sum absolutely $v_1 + v_2$, so we will accept no error. The complete multiplier ambit is the following:

where the achievement voltage is accustomed :$v_ = - left\left( - frac - \left(v_1 + v_2\right) + \left(v_1 + v_2\right)$
ight) = frac

thats absolutely what we wanted. The ambit works as continued as the afterward accord is verified:

:$v_1 , v_2 > - R I_s$

so the inputs can be aught or admirable abrogating but, back $R I_s$ will be a baby voltage, we are accustomed to carbon the affiliation artlessly as $v_1 , v_2 geq 0$. From the algebraic point of appearance this is due to the actuality that we deceit account the logarithm of a abrogating number, from a concrete point of appearance the absolute is due to the actuality that we can access alone actual baby currents (almost zero) inverse-polarizing the diodes.

In applied applications, the diodes are replaced with BJTs affiliated so to plan like a diode.

Since it is accessible to use a MOSFET transistor as a voltage controlled resistor, we can use this affection to make an analog multiplier.

Let us accredit to account on the right. With the letter we announce the altered pins: Drain, Antecedent and Gate. MOS are balanced devices, so we could alter the cesspool with the antecedent after affecting the behavior of the device. Anyhow able-bodied alarm antecedent the everyman voltage pin and cesspool the point with the accomplished voltage. If the voltage amid aboideau and antecedent is beneath than the voltage amid cesspool and source, i.e. $V_ < V_$, the accord amid accepted and voltage is the following:

:$I_ = K \left[2 \left(V_ - V_T\right) V_ - V_^2\right] simeq 2 K \left(V_ - V_T\right) V_; qquad V_ < V_$

assuming we can consistently use this relationship, the analog multiplier agreement is the following:

where antecedent and cesspool of both accessories are acicular out. If $v_2$ and $V_$ are positive, then the sources will abide there because that credibility are around affiliated to arena by the operational amplifiers. The accepted abounding through $R_1$ is defined: one ancillary of the resistor has the voltage $v_1$, the additional one is grounded. That aforementioned accepted will breeze through the MOS $M_1$, appropriately defining the voltage $V_G$. The accepted is accustomed :$frac = - I_ = - 2 K \left(V_ - V_\right) V_$

but $V_ = V_G$ and $V_ = V_$. replacing and artful we get:

:$V_G = V_ - frac$

considering the additional MOS $M_2$ we have:

:$; I_ = 2 K \left(V_ - V_\right) V_$

where $V_ = V_G$ and $V_ = v_2$.

Replacing we get:

:$I_ = - frac$

from which we assuredly get the achievement voltage:

:$v_ = frac frac; qquad V_, v_1, v_2 > 0$

and this is what we wanted. The aberration amid the antecedent configurations are:

In additional words, the diode accomplishing is added complicated but it works accomplished for a added ambit on inputs.

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